1. Field of the Invention
This invention relates to electronic frequency dividers and more specifically to a frequency divider comprising a voltage-controlled ring oscillator having multiple phase-shifted outputs, an integer logical divider, and a signal combining circuit.
2. Description of the Background Art
As computers, especially personal computers, gain in functionality, they impose greater requirements on data storage devices such as hard disk drives. Because of the greater running speeds of today's computers, today's disk drives must likewise operate faster. To facilitate fast data access, many hard disk drives implement a 1/7 encoding format. The use of this format requires that two clock signals be generated: a first clock signal (hereinafter, "data rate signal") which has the same frequency as the desired data rate, and a second clock signal (hereinafter, "higher frequency signal") which, because of coding requirements, has a frequency 1.5 times that of the data rate.
These clock signals could be generated separately by individual clock generators, but it would be very difficult if not impossible to synchronize the two separate signals. For this reason, the two required clock signals are usually generated using a single clock source. The higher frequency signal is typically generated by a voltage-controlled oscillator (VCO), and the data rate signal is derived from the higher frequency signal by performing a "logical divide by 1.5" operation on the higher frequency signal to obtain a signal having a frequency equal to the higher frequency divided by 1.5. The difficult aspect of this process is the implementation of the logical 1.5 divider.
The prior art has used several methods to implement the logical 1.5 divider. One method requires that a first signal be generated by a VCO having a frequency equal to 1.5 times the desired data rate. Then, every third clock pulse is deleted from this first signal to provide an output signal having an effective frequency equal to the frequency of the first signal divided by 1.5. Hence, the data rate signal is derived. While this method does generate a data rate signal having the correct number of clock pulses, the resulting signal is non-symmetrical. That is, while the number of clock pulses is correct, the duration of each clock pulse is the same as if the pulse had been from the higher frequency signal. This in effect forces the controller integrated circuit (which is driven by this clock signal) to respond with the same speed as if it were being driven by the higher frequency signal. Thus, even though the nominal frequency of the signal is correct, the controller effectively operates as if it were being driven by the higher frequency signal.
Another prior art method requires that a VCO generate a first signal having a frequency three times that of the desired data rate. The data rate signal is derived from the first signal by using a logical divide-by-three circuit, and the higher frequency signal is derived from the first signal by employing a divide-by-two circuit. The result is that the higher frequency signal has a frequency which is 1.5 times that of the data rate signal. A problem with this method is that it requires the VCO to generate a signal having a frequency three times that of the data rate. The frequencies that a VCO can generate are limited. Currently, it is difficult for any VCO to generate signals having frequencies much higher than 60 MHz. This would means that the data rate signal may only have a frequency of approximately 20 MHz. This imposes a significant and undesirable limitation on the rate of data transfer.
Therefore, there exists a need for a logical 1.5 divider which provides a symmetrical output signal without needing to generate a signal having a frequency three times that of the data transfer rate.